The present invention relates to an error rate monitor providing a non-linear measurement response.
In conventional digital communication systems comprising data transmission lines, data streams flowing along the lines are often partitioned into fixed-length blocks of data. Each block contains data for transmission together with some additional overhead information. This overhead information can, for example, include a simple parity bit, a more comprehensive bit-interleaved word or a sophisticated coding algorithm, the information being useable for determining an estimated error count for its associated block.
Bit error rate monitoring of the streams in the systems is performed by collating error occurrence records derived from overhead information associated with the streams. Such error rate monitoring is important because data transmission lines of the systems operable to convey data streams are often hired out to customers at a premium rate on the basis of there being low error rates on the lines; customers are often interested to measure error rate to ensure that they are not paying the premium rate unnecessary or to ensure that they can receive a discount if the transmission lines are below standard.
Most conventional digital transmission systems operate at a relatively low bit error rate of less than 1 error in 106 bits in their respective data streams. However, error bit rates of 1 error in 104 bits of data in their respective data streams can be encountered on occasions. It order to monitor such errors, blocks of data are typically partitioned in a range of 100 to 1000 bits in size; this range is kept to a relatively low number of bits in order to reduce system hardware complexity and improve error rate monitoring at high error rates, for example 1 error in 104 bits of data.
In order to obtain acceptable statistical estimates of bit rate error, block errors are counted over a sufficiently large number of blocks to yield a few tens of errors; for 100-bit blocks, an error rate of 1 error in 106 bits corresponds to, on average, one error every 10000 blocks. To obtain a good statistical estimate of current bit error rate, block errors have to be counted over 300000 blocks to yield a few tens of errors.
In practice, digital error rate monitors are needed which are capable of supplying reasonably accurate error estimates over a wide range of error rates from 1 error in 104 bits to 1 error in 1010 bits. Such a wide range corresponds to a range of one to one million and is far greater than individual conventional error rate monitors and associated detection algorithms can accommodate. Thus, conventional error rate monitors adapted for measuring over such a wide range comprises a set of several monitor units, usually one unit allocated for monitoring a decade range in the overall wide range.
The inventor has appreciated that it is possible to devise an alternative error rate monitor which can accommodate a wide range of error rates without a need for there to be multiple monitor units included therein, thereby reducing cost and complexity of transmission systems incorporating such alternative monitors compared to them including equivalent conventional error rate monitors.
According to a first aspect of the present invention, there is provided an error rate monitor for measuring rate of error occurrence in a data stream, the monitor characterised in that it includes:
(a) error detecting means for receiving the data stream and analysing it to identify when errors occur therein;
(b) counting means for counting up errors identified by the detecting means to provide a cumulative error count; and
(c) decrementing means for decrementing the error count at a rate dependent upon the magnitude of the error count,
the decrementing means operable to decrement the error count at a rate which increases more than linearly with respect to increases in the magnitude of the error count, the error count thereby providing an indication of error rate within the data stream.
The invention provides the advantage that the error count increases less than linearly with respect to increasing error occurrence thereby providing the monitor with an enhanced measuring range.
Advantageously, the rate at which the decrementing means decrements the error count increases substantially exponentially with respect to increases in the magnitude of the error count, thereby providing the monitor with a substantially logarithmic response for the error count with respect to error occurrence in the data stream. The substantially logarithmic response provides the benefit of a relatively large dynamic range for the monitor of the invention; conventional monitors typically provide a linear measurement response.
Preferably, the data stream is partitioned into data blocks, each block having associated therewith overhead information useable by the error detecting means for determining error occurrence in the block. Such partitioning enables the counting means and the decrementing means are clocked at a rate depending upon a rate of receipt of data blocks at the error detecting means. The monitor thereby is rendered capable of coping with varying rates of receipt of blocks at the detecting means and therefore determining error rate in the data stream taking such varying rates into account.
In one embodiment of the invention, the detecting means, the counting means and the decrementing means are implemented in the form of processing means executing software. Such an implementation of the monitor is convenient when the monitor is used in communication systems primarily comprising interlinked computer networks.
In another embodiment of the invention implemented in hardware form, the error detecting means conveniently includes an assembly of logic gates operable to detect errors in the data stream, the counting means includes an up/down counter for counting errors detected by the detecting means and for providing a count output, and the decrementing means includes a binary counter and a multiplexer for providing data for use in decrementing the up/down counter depending upon the magnitude of the count output, thereby rendering the count output indicative of error rate in the data stream. Such an implementation of the monitor is relatively simple and can be integrated onto a single integrated circuit. For example, the monitor can be implemented such that the up/down counter is a 4-bit up/down counter, the binary counter is a 16-bit binary counter and the multiplexer is a 16-to-1 multiplexer. When implemented in such a manner, the count output of the up/down counter is preferably connected to address inputs of the multiplexer for selecting count outputs of the binary counter for use in generating the data for use in decrementing the up/down counter.
In a second aspect, the invention provides a communication system including communications paths operable to convey respective data streams, one or more of the paths each including a monitor according to the first aspect of the invention for monitoring error rate along the path. Inclusion of the monitor of the first aspect of the invention enables error rates occurring in the paths to be monitored over potentially a relatively wide range of error rates. The system is advantageously operable to divert data streams away from paths whose associated monitors detect an excess rate or error occurrence; such operation is capable of providing users of the system with more reliable communication.
In a third aspect, the invention provides a method of measuring error occurrence in a data stream using a monitor according to the first aspect of the invention, the method including the steps of:
(a) detecting error occurrence in the data stream;
(b) incrementing a cumulative error count in counting means of the monitor when errors occur in the data stream;
(c) decrementing the error count at a rate dependent upon the magnitude of the error count; and
(d) repeating steps (a) to (c) until monitoring of error occurrence is completed, the error count being indicative of a rate of error occurrence in the data stream.